发明名称 TEST CIRCUIT
摘要 PURPOSE:To eliminate an fault to the increase of the number of process bits, by incorporating a circuit which checks an ROM or an internal function into an LSI and utilizing a test pin for the user to load some function to the pin. CONSTITUTION:A shift register 2 which shifts the reset signal of a reset input terminal 1 by n bits plus a deciding circuit 3 which supplies the output signal of the register 2 with a shift of n bits and another output signal received a shift of <=n bits are provided to a single chip CPU in an LSI. At the same time, a shift clock is added to the register 2. Then a user uses the terminal 1 of the register 2, and an internal resetting signal 31 is outputted from the circuit 3 when a reset input signal of >=n bits is applied. Then a test working signal 32 is outputted to an reset input signal of <=n bits to cope with the increase of the process bits.
申请公布号 JPS5769347(A) 申请公布日期 1982.04.28
申请号 JP19800141336 申请日期 1980.10.09
申请人 NIPPON DENKI KK 发明人 TOYOFUKU TAKASHI
分类号 G06F11/22;G06F1/24;G06F11/273;G06F12/00 主分类号 G06F11/22
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