发明名称 TIMER CIRCUIT
摘要 PURPOSE:To simplify the circuit constitution, by detecting a voltage of a capacitor constituting an integral network with an inverter having hysteresis characteristics and obtaining the delay time of operation and restoration. CONSTITUTION:When an input signal A is at L level, a transistor (TR)2 is non- conductive, a capacitor 8 is charged, and an output (c) of an inverter 24 is at L level. When the input signal A is at H level, the TR2 is turned on and the charge of the capacitor 8 is discharged through a resistor 5. When a terminal voltage (b) of the capacitor 8 reaches a threshold voltage VL of the inverter 24, an output (c) is at H level. When the input signal A is again at L level, the TR2 is turned off, the capacitor 8 is charged via resistors 4, 5, and when the voltage (b) reaches a threshold voltage VH of the inverter 24, the output (c) is at L level.
申请公布号 JPS5776922(A) 申请公布日期 1982.05.14
申请号 JP19800152468 申请日期 1980.10.29
申请人 MITSUBISHI DENKI KK 发明人 ODA SHIGETOU
分类号 H03K5/04;G04F3/00;H03K17/28;H03K17/296 主分类号 H03K5/04
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