| 摘要 |
PURPOSE:To switch a video signal of different bus lines in the same timing as a vertical synchronizing pulse, by providing a buffer register between a register corresponding to a control data signal of a computer and a switching register. CONSTITUTION:A control data signal applied by a plurality of times from an output port of a computer is set to a register 208 during one period of a vertical synchronizing pulse, an upper-order 4-bit control data signal is decoded and BUS lines up to 16 lines are designated, and lower-order 4-bit control data signal is stored in buffer registers 203 and 206 provided at each BUS. An output signal of the buffer registers 203 and 206 sets switching registers 202 and 205 provided at each BUS in the same timing with the pulse VP. An output signal of the registers 202 and 205 is decoded with decoders 201 and 204 and a video signal on a pluraity of lines is selected with the same timing in vertical synchronism by controlling the cross point of video switching. |
