发明名称 FREQUENCY-DC VOLTAGE CONVERSION CIRCUIT
摘要 PURPOSE:To eliminate generation of error in output due to external noises and so on even in the state that frequency signal is not being applied by using a delay circuit that outputs output signal that delays by a certain time the output of trigger signal circuit in place of an integrating amplification circuit. CONSTITUTION:Input alternating signal FIN is input to a trigger signal circuit 1 to generate trigger output. The trigger output is applied to an one-shot circuit 2 and a delay circuit 7. Here output that operates trigger output with a delay of certain time is out from the trigger circuit 7, and this output is input to a bias circuit 8. The output from the one-shot circuit 2 and the output from the bias circuit 8 are added in an integrating circuit 6, and it is output further through an averaging circuit 3.
申请公布号 JPS57160069(A) 申请公布日期 1982.10.02
申请号 JP19810046649 申请日期 1981.03.30
申请人 TOKYO SHIBAURA DENKI KK 发明人 AZUMA SHINOBU;NODA KIYOSHI
分类号 G01R23/06;(IPC1-7):01R23/06 主分类号 G01R23/06
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