发明名称 VERTICAL DEFLECTING CIRCUIT
摘要 PURPOSE:To prevent the generation of lateral white noise on the screen of an image display while preventing interference other circuit blocks, by constituting a circuit in such a way that plural transistors (TR) are not turn on and off in a period other than a blanking period. CONSTITUTION:A signal VA from a vertical oscillating circuit 1 is applied to a flip-flop (F-F)19 through a switching TR16. When the VA is positive, the TR16 turns on, and a TR18, therefore, turns off. At this time, a TR20 turns off and the capacitor 6 of a charging and discharging circuit 7 is charged. When the capacitor 6 is charged up to the 1st reference voltage V2, a comparator 22 outputs a voltage VF and when up to the 2nd reference voltage V1, a comparator 21 operates turn on a resetting TR23 immediately and the FF19 is inverted to turn on the TR20, so that the capacitor 6 is discharged. Said operation is repeated to obtain a blanking signal at an output terminal 13 and a deflection driving pulse at an output terminal 27.
申请公布号 JPS57183181(A) 申请公布日期 1982.11.11
申请号 JP19810069179 申请日期 1981.05.07
申请人 SANYO DENKI KK;TOKYO SANYO DENKI KK 发明人 KISHI HIROYASU
分类号 H04N3/16;H04N3/24;(IPC1-7):04N3/16 主分类号 H04N3/16
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