| 摘要 |
PURPOSE:To shorten a synchronizing stable time, by detecting phase against a frequency source by a phase detecting pulse obtained from inside of a frequency divider, generating an inverted pulse from a gate circuit when being about >=90 deg. out-of-phase with stable phase, and reversing phase in accordance with magnitude of a phase shift. CONSTITUTION:Frequency within a constant range is oscillated by a VCO13 constituting a part of a PLL circuit, an output of an LPF12 is compared with voltage of reference voltage 14, and oscillation frequency is varied to >=2 times a frequency source 14. An output of this VCO13 is frequency-divided to frequency being close to the frequency source 14 by a frequency divider 16, the output in case when the frequency is being divided is provided to a phase comparator and detector 17 as a reference pulse 19, the pulse 19 and the frequency source 14 are compared with each phase by the detector 17, and in case of >= about 90 deg. and <=270 deg. out-of-phase, an inversion instructing pulse is provided to an invertor. Subsequently, the frequency source 14 and an output of the invertor 18 are compared to each phase by a phase comparator 1, a pulse of width having only a phase difference portion is outputted, is provided to the VCO13 through the LPF12, and the synchronizing stable time is shortened. |
