发明名称 MEMORY CONTROLLER
摘要 <p>PURPOSE:To speed up the execution of cutout and synthesis without path neck, by calculating the address of data to be transferred based on the length of required part and not required part of head address storing two-dimensional picture scanning data. CONSTITUTION:An address switch 10 of a memory controller 5 transmits data transmitted from an address bus 6 to a memory 4 when a mode selection signal 50/ transmitted from a control section 30 indicates the mode 1(a mode using a memory 4 as a main storage device of a central processor 3). When the signal 50/ indicates the mode 2(a mode using a memory 4 as a cutout/synthesis device of a partial diagram), a data 507 transmitted from an address controlling section 20 is transmitted to the memory 4 as an address data. The address controlling section 20 calculates the transferred address and transfer address at the mode 2.</p>
申请公布号 JPS584470(A) 申请公布日期 1983.01.11
申请号 JP19810101238 申请日期 1981.07.01
申请人 HITACHI SEISAKUSHO KK 发明人 MACHIDA TETSUO;TSUHARA SUSUMU;TABATA KUNIAKI;OKADA YASUYUKI
分类号 G11C7/00;G06F12/02;G06F13/28;G06T1/60;G06T3/00 主分类号 G11C7/00
代理机构 代理人
主权项
地址