| 摘要 |
PURPOSE:To speed up an access time and to decrease power consumption, by apparently varying a gm of a load transistor with information at accessing and controlling steady-state current according to the said information. CONSTITUTION:Level converters LC1 and LC2 respectively receive logical signals on a bit line BL and convert the level and the result is applied to each control electrode of load transistors (TR) Q1 and Q2. When a memory cell MC is accessed with a word line WL with a TRQ5 at L and a TRQ6 at H level, first a current rises. Before this current rises, the logical level of the line BL is not sufficiently lowered to L level, rather at H level. The level H of the line BL is converted for the level sufficiently with the level converter LC1 and a sufficiently high H level is applied to the gate of the TRQ1. |
