| 摘要 |
In a non-restoring divider circuit each divider step is completed in a single clock pulse by comparing the most significant bits and utilizing a continuous type of comparison to gate data into adding circuits, the summation output of which is introduced into the next most significant gate of the numerator to replace the data previously in the numerator with shifted summation data. Prior to the dividing operation the bits in the three most significant stages of the denominator are compared and the data in the shift registers is shifted by two spaces each clock pulse until the comparison indicates that the data is normalized or until a single clock pulse will complete the normalization of the data.
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