| 摘要 |
A decoder circuit for a semiconductor memory device includes a plurality of input terminal gates for receiving address signal bits and for producing the same signal as well as inverted signals thereof; first decoder lines for decoding output signals of some of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the first decoder lines, and of which another terminal is connected via a resistor to a power source and to the base of transistors which drive a group of output terminal gates. The diode matrices or multi-emitter transistors being capable of turning the transistor on or off depending upon the potential of the first decoder lines. The decoder circuit provides second decoder lines to which are connected constant current sources; emitter follower-connected transistors which are inserted between the power source and the second decoder lines, and which are turned on or off by the output signals of the remainder of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the second decoder lines, and of which another terminal is connected via a resistor to the emitter of the transistor for driving the group of the output terminal gates and to the base of an output transistor. The diode matrices or the multi-emitter transistors being capable of turning the output transistor on or off depending upon the potential of the second decoder lines and upon the emitter potential of the transistor which drives the group of the output terminal gates.
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