| 摘要 |
PURPOSE:To realize an efficient application of a vector processor, by securing the execution of subsequent vector instructions although the execution of a vector macroinstruction is not over. CONSTITUTION:A VSMS instruction is shifted to a register 13, and queuing registers 16-1 and 16-2 are idle. In such a case, an instruction is accepted, and the register 16-1 contains the decoding information on a storing action. While the register 16-2 has the information on a summing action. At the same time, a flag 20 is turned on. While the flag 20 is kept ON, the start of the instruction is inhibited for the register 16-1. Then a SUM action is started first, and a processing part 6 starts to open the register 16-2. When the SUM action is over, the storing action is possible. When a VM instruction is set in a queuing mode of the storing action, the 1st operand register number is compared with the input/ output operand register numbers of registers 16-1 and 16-2. Then the VM instruction is put into the idle register 16-2 when no coincidence is obtained from the above-mentioned comparison. The storing action of the register 16-1 is started if a multiplier is idle since the storing action is impossible to start. |
