| 摘要 |
PURPOSE:To reduce the capacity of the periphery of gates by a method wherein a low impurity density region forming a gate is formed in a stepwise or gentle distribution of density, then the density of surface side is relatively enhanced, thus gate intervals are narrowed, and the density immediately under the gate is reduced, or set to an intrinsic semiconductor layer. CONSTITUTION:When a SIT of flat gate structure is manufactured, first an N<-> layer or an intrinsic semiconductor layer 113 is grown on a P type layer 11, and an N<+> type layer 13 is deposited thereon. Next, a ring P type region 14 is diffusion-formed in the layer 13, and a shallow N<+> type region 12 is provided in a channel region surrounded thereby. Thereafter, an anode electrode 1 is mounted on the back surface of the substrate 11, a cathode electrode 2 on the region 12, and a gate electrode 4 on the region 14, respectively. To obtain the SIT of step cut type structure, the N<+> type region 13 and the N<-> type region 113 are provided in the N<-> type layer to form a channel, and then the P<+> type region 14 is formed in the region 13. Thus, a SIT which performs a high speed operation and a low consumed power operation is obtained. |
