发明名称 DELAY CIRCUIT
摘要 PURPOSE:To use memories of lower speed than a conventional memory and to adopt common arithmetric devices for the circuit, by providing an arithmetic means for calculating an output signal of a storage means for constituting the circuit to obtain plural delay signals in the unit of period to an input signal with respect to a picture signal such as television signal. CONSTITUTION:An input signal VIDEO is applied in common to data input terminals of line memories 31-34, each output signal from data output terminals of the line memories 31-34 is supplied to the data input terminals of the arithmetric devices 35-38, and each output signal from the data output terminals of the arithmetric devices 35-38 is connected to each contact of changeover switches SW1-SW3. A signal L1 operated with 1H delay to the input signal VIDEO is read out from the line memory 32 and a signal L2 is read out from the line memory 33 at the selected contact position of the changeover switches. Further, the delay in 2H, 3H corresponds respectively to the line memories 32, 31 and output signals L1-L3 are extracted so as to keep a constant delay time.
申请公布号 JPS594217(A) 申请公布日期 1984.01.11
申请号 JP19820113528 申请日期 1982.06.29
申请人 MATSUSHITA DENKI SANGYO KK 发明人 IRIE KAZUAKI
分类号 H04N5/14;H03H11/26 主分类号 H04N5/14
代理机构 代理人
主权项
地址