| 摘要 |
PURPOSE:To detect surely a control signal in high speed, by exlucing the detecting output of a signal corresponding to a frequency of the control signal detected at a picture signal transfer period. CONSTITUTION:When a detecting circuit 6 detects the frequency of the control signal (f) or (h), a signal dt is given to a CPU7 which reads the count value of a counter 61. A signal sh rises in the leading edge timing of a synchronizing signal syh at the CPU7. An inverter 52 of a synchronizing signal detecting circuit 5 outputs a signal V3 and the Q output is a high level so long an no reset signal is applied. Even if an FF is reset depending on the detection of the control signal at the receiving period, the FF is already set when the synchronizing signal falls down. The CPU7 recognizes that the detected output of the detecting circuit 6 is not the control signal. The CPU7 resets an FF51 with the detected output of the detecting circuit 6 and discriminates the Q output after a prescribed period. That is, even if an FF51 is reset during the control signal period, since no falling signal exists from the inverter 52, the FF51 is not set. Thus, the receiving signal is discriminated from the Q output by the CPU7. |
