发明名称 TIME DIVISION INTEGRATED COUNTER
摘要 PURPOSE:To reduce the mounting space and to simplify the hardware, by obtaining a counter output subjected to time division at each channel with an output latching a counter output stored temorarily in an RAM. CONSTITUTION:A channel designation signal fd is sent to a scanner 16 and an RAN 12 from a channel forming counter 20 with a timing signal TM1 issued from a timing circuit 18, and a scanner 16 outputs ''0'' or ''1'' to an ROM 10 by the presence of the counter input. Further, the ROM 10 produces a counter output as the firmware based on this signal and a feedback signal Inf. Then, the outpt of the ROM 10 is written in the RAM 12 with a timing signal TM3 and read out and then sent to a latch circuit 14. Then, the latch output of a circuit 14 outputs a counter signal P subjected to time division at each new channel.
申请公布号 JPS598434(A) 申请公布日期 1984.01.17
申请号 JP19820117581 申请日期 1982.07.06
申请人 MEIDENSHA KK 发明人 KURIMOTO TAKATSUGU;MATSUDA TSUTOMU
分类号 H03K21/02;H03K21/00;(IPC1-7):03K21/00 主分类号 H03K21/02
代理机构 代理人
主权项
地址