| 摘要 |
PURPOSE:To reproduce a clock, by adding a binary train in which 1 and 0 are alternately continue to another binary data train in a mode 2 and inverting 1 and 0 of the binary train in case (n) units of 1 or 0 are continuous in the data on the result of addition. CONSTITUTION:An NRZ signal (a) supplied from an input terminal 301 is added with a 1/0 continuous inverting signal (f) at an exclusive OR gate 302 and in a mode 2. This output signal C receives an exclusive OR to a 1/2T delay circuit 303 at a circuit 304 to obtain an output signal (g). The signal (g) resets an n-notation counter 305 with a pulse signal corresponding to an inverted area of the signal C. The signals supplied from a clock terminal 306 are counted by the counter 305. then a flip-flop 307 is triggered every 5 continuous pulses, and the output (e) supplies the phase of a 1/0 continuous inverting signal (b) to the gate 302 after selecting a gate 309 or 310. As a result, a inverted signal is always obtained at an output (h) for the next signal if 5 units of 1 or 0 are continuous. |
