| 摘要 |
PURPOSE:To cut off electrically a procesor of the post-stage, by monitoring a control voltage of a voltage controlled oscillator of a PLL, stopping a clock when the control voltage is not within a prescribed range and bringing a receiver output to a high impedance. CONSTITUTION:A PCM signal transmitted optically is received at a photo detector 1, converted into an electric signal, amplified 2 and inputted to a discriminating regenerative device 7, and a synchronizing signal is inputted to a phase comparator 3. A PLL is constituted of the comparator 3, a voltage controlled oscillator 5 and a filter 4, the regenerative device 7 discriminates and regenerates the normal data by the synchronizing signal from the oscillator 5, outputs the data via a tri-state buffer TSB8 and outputs the clock via a TSB9. A level monitor 6 monitors an output voltage Vd of the filter 4 and transmits a control signal to the TSBs 8, 9 when the out of synchronism of the oscillator 5 takes place because of the voltage Vd at the outside of the specified range due to the deterioration in the receiving level, brings the output of the TSB to a high impedance, the data and clock are cut off and the alarm is transmitted to the processor of the post-stage. |
