| 摘要 |
PURPOSE:To enable to reduce the collector-base junction capacitance and the emitter-base junction capacitance by decreasing the area of the base by a method wherein the vertical part in a poly Si part which forms an emitter structure is utilized and then formed into an emitter width. CONSTITUTION:A buried collector layer 2, an epitaxial layer 4, and an isolation insulation film 3 are formed on a P type substrate 1, and As is implanted by forming an insulation film 7 and a poly Si 11. The poly Si 11 and the insulation film 7 as an oxide film are vertically etched by reactive ion etching RIE, thus leaving only the poly Si serving as an emitter lead-out region, and thus the poly Si is removed by etching. A part of the Si 11 and the region serving as the collector are covered with a resist 18, boron is implanted, and the entire body is covered with a poly Si 11a by heat treatment. Next, anisotropic etching by RIE is performed, and accordingly the poly Si in the vertical direction left at this time is formed into the emitter width. Then, As diffuses into the Si as the emitter by heat treatment, resulting in the formation of the base 5 immediately under the poly Si and the emitter 6 diffused at this time in self-alignment. |
