发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To contrive the speed-up of a circuit element and the reduction of consumed power by a method wherein a MOSFET and a bi-polar transistor are effectively combined and thus made composite. CONSTITUTION:An N-epitaxial layer 53 on a P type substrate 51 wherein an N- layer 52 is burned is isolated by a P layer 521, and a P layer 56 is formed by ion implantation via a thermal oxide film 520. Oxide thick films 57 are provided by Si3N4 masks 522, and an N<+> layer 523 is connected to a layer 52. The masks 522 and the film 520 are removed, gate oxide films 524 and poly Si gates 525, 526 are formed, and P layers 54 and 55 are formed by applying a mask 527. N layers 58, 59, and 510 are formed by masking the part of a P-MOS Q1, and Q1, Q2, Q3 are completed by protecting the gate electrodes 525 and 526 with oxide films 512 and 513 and then by attaching metallic electrodes. This constitution enables to lead out a drive current larger than by an inverter circuit with single CMOS from an emitter terminal; therefore high speed actions can be expected.
申请公布号 JPS5968962(A) 申请公布日期 1984.04.19
申请号 JP19820178412 申请日期 1982.10.13
申请人 HITACHI SEISAKUSHO KK 发明人 NAKAMURA TOORU;HONMA NORIYUKI;HORIUCHI KATSUTADA
分类号 H01L29/78;H01L21/8249;H01L27/06 主分类号 H01L29/78
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