发明名称 ANALOG-DIGITAL CONVERTER
摘要 PURPOSE:To attain the conversion with high accuracy and speed by applying negative feedback control to the maximum power of an integrating circuit in parallel with A/D conversion so as to make the count value coincident with a full scale of the counter. CONSTITUTION:The converter is in the waiting mode at a period T1. A switch 150 is closed to the position (a) at a period T2, and when a current is applied from a capacitor 70 from a variable constant current source 10, a counter 40 starts counting at the same time. When a voltage of the capacitor 70 reaches Vi, an output of a comparator 20 changes from 1 to 0, and the count value in this case is held at a latch circuit 50. A switch 250 is changed over to the position (b) at the same time, and when the voltage of the capacitor 70 reaches a voltage Vref, the output of the comparator 20 changes from 1 to 0, and this change is transmitted to a T-V converting circuit 30. When the value of the counter 40 reaches 2n, this timing is given to the converting circuit 30 and the shift between said timing and the integrating time is compensated. Since the converting operation and calibrating operation are performed at the same time, the conversion is attained with high accuracy and at high speed.
申请公布号 JPS5985128(A) 申请公布日期 1984.05.17
申请号 JP19820194674 申请日期 1982.11.08
申请人 HITACHI SEISAKUSHO KK 发明人 KATOU KAZUO;SATOU HIDEO
分类号 H03M1/10;H03M1/56 主分类号 H03M1/10
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