| 摘要 |
PURPOSE:To attain a high-speed sorting operation by performing the fetching and comparison in magnitude between the data on a data bus to be written from now and the data so far held simultaneously, at every memory circuit in parallel. CONSTITUTION:When the data is written from an external CPU, the data to be written is put on a data bus DB and a data writing signal WT is transmitted. A comparator 12 compares the data held at a memory part 11 and the data on the bus DB and then transmits the result signal Ci of comparison to a control part 13. The part 13 contains a signal Ci-1 obtained by comparing the data through a memory circuit of the preceding stage in the same way as the signal Ci. When the signal WT is supplied, the part 13 controls the part 11 based on the signals Ci and Ci-1. Then the part 11 fetches the data on the bus DB. |
