| 摘要 |
PURPOSE:To provide both functions of an edge trigger FF circuit and a level trigger FF circuit by enabling a data to be inputtd by both of a clock of an edge trigger type and a clock of a level trigger type. CONSTITUTION:An output terminal of an OK circuit 2 is connected to a clock input terminal 1C of the level trigger FF1. The connection is made that a level clock sigal 2C and a pulse signal 3P of a prescribed width formed in the timing of the leading of an edge clock signal 3C are applied to input terminals of the circuit 2. Thus, in adjusting suitably a delay time of a delay circuit 4, a data signal D inputted from a data input terminal 1D at the leading edge of the signal 3C is fetched to the FF1 and an output 1Q is decided. Further, when the signal 2C is inputted to other input terminal of the circuit 2 and the signal 2C is at ''1'', the FF1 fetches a data signal D. Thus, the FF1 fetches the data at the input terminal 1D by the signal 2C and the signal 3C. |
