发明名称 SPARE COLLATION SYSTEM
摘要 PURPOSE:To perform the collation between the using and spare systems in a waiting time during which a frame synchronizing signal is extracted, by reading out the data of a memory circuit of the in-use system by a memory selection signal obtained by shaping the frame synchronizing signal, then writing the data into a memory circuit of the spare system. CONSTITUTION:The in-use systems 2'-1-2'-n containing memory circuits 6'-1- 6'-n which are replaced every several frames of a digital signal are successively selected. Then the same digital signal is supplied to each of spare systems containing the memory circuits 6' having the same function as the selected in-use system. In this spare collation system, the digital signals written to the circuits 6'-1-6'-n of the using system are written in parallel to the circuits 6' of the spare system by means of a memory selection signal obtained by shaping the frame synchronizing signal of the digital signal. The supplied digital signal is supplied to each of the in-use and spare systems synchronously by a control signal.
申请公布号 JPS59119940(A) 申请公布日期 1984.07.11
申请号 JP19820232621 申请日期 1982.12.25
申请人 FUJITSU KK 发明人 MORIMOTO AKIO;SUDOU MAKOTO;IYOTA TOSHIO;HASHIMOTO KENICHI;TAKEUCHI HIROYUKI
分类号 H04L1/22;(IPC1-7):04L1/22 主分类号 H04L1/22
代理机构 代理人
主权项
地址