| 摘要 |
1,045,314. Field effect transistors. S. TESZNER. Aug. 4, 1964 [July 26, 1963], No. 30972/64. Heading H1K A field effect transistor comprises a semiconductor wafer of one conductivity type with a layer at one face including source and drain and interconnecting channel regions all of the opposite conductivity type. The channels, which extend in the plane of the layer, are preferably of approximately triangular section, bounded on one side by the wafer-layer interface and on the remaining sides by semi-cylindrical regions of the same conductivity type as the wafer, which extend from the layer surface to the interface. The source and drain regions may be parallel strips as in Fig. 4 with the channels perpendicular to them. Alternatively they are in the form of circular, rectangular or square frames (Fig. 8). The devices are preferably formed by gaseous diffusion from boron trioxide through an oxide mask into a high resistivity N-type surface layer on a P+ silicon wafer. The diffusion forms the half cylindrical gate regions 3 (Fig. 4) which extend to the wafer material and are joined at the surface. The source and drain regions are bounded by further diffused regions 11a and 11b which are connected to the gate regions through the wafer. Ohmic source and drain contacts are provided, preferably on areas pre-diffused with phosphorus by evaporation of gold-antimony through a mask followed by alloying. The gate contact may be made to the back of the wafer, or to the surface of any of regions 6, 11a and 11b. The Fig. 8 arrangement comprises two devices with a common connection to gates 25, 26. They may be operated in series using contacts 32, 34 as source and drain or in parallel with 32, 34 as sources and 30 as common drain.
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