| 摘要 |
<p>PURPOSE:To attain low power consumption by performing the column selection at charging and the column selection at read by a common column address line so as to perform read operation after the end of charging. CONSTITUTION:A charging clock phip is at power supply potential, the 2nd column address line C2 is at power supply potential, row address lines R1-Rn and the 1st column address lines C11-C1m are at ground potential, and a node 3 being an output terminal of an NOR gate G11 is at ground potential at the initial state. The charging clock phip and the 2nd column address line C2 are decreased to ground potential to charge a node 2. One line of the 1st column address lines C11-C1m rises to the power supply potential with delay from the phip and the C2 and one of data read lines D1-Dm is charged through one of N channel MOSFETs N1-Nm. When the charging is finished, the charging clock phip restores to the power supply potential, the P channel MOSFETP1 is turned off, one of the column address lines R1-Rn rises to the power supply potential, one of the memory cells M11-Mmn is selected so as to discharge the data read line and the node 2 depending on the storage state of the memory cell.</p> |
