| 摘要 |
PURPOSE:To miniaturize the chip area at circuit integration and to reduce the read time of data by setting a potential of a data line to an intermediate potential between potentials corresponding respectively to ''1'' level and ''0'' level of the data before the data is read from a memory cell. CONSTITUTION:A clock pulse phiB goes to ''1'' level before data read at first. In this case, since a clock pulse phi'B is at ''0'' level, MOSFETs 43, 41 in a potential set circuit 40 are turned on. The MOSFET41 is turned on, causing a data line 12 to be charged rapidly to VDD at first. Further, the MOSFET43 is turned on, causing a circuit point 42 to be discharged rapidly up to VSS. When the period of the clock pulse phiB is elapsed, a clock pulse phiA goes to ''1'' level this time. Since a clock pulse phi'A is at ''0'' level in this case, MOSFETs 44, 45 in the potential set circuit 40 are both turned on. |
