发明名称 PRIORITY DECISION CIRCUIT
摘要 PURPOSE:To eliminate the bias of assigment of priority by giving a serial number to plural processing requests and providing a circulating circuit including the serial number to assign uniformly the priority to requests. CONSTITUTION:In deciding the priority of plural processing requests 5, a number represented by a counter 3 and a signal from a decoder 4 are collated by a collating circuit 7, and when they are coincident, the coincident number is preserved. Assuming a processing request decided the priority as l, then when the internal processing as to the l is finished, an end signal is given to an REQ1 from the inside of the device, and the REQ1 is incremented by +1 or decremented by 1. If other request exists after the end signal is issued, the priority decision circuit is operaed by l+1 and l-1 immediately. Thus, the probability of the processing receiving is averaged among plural requests to a processing request arisen asynchronizingly.
申请公布号 JPS59158444(A) 申请公布日期 1984.09.07
申请号 JP19830032117 申请日期 1983.02.28
申请人 FUJITSU KK 发明人 MASUDA JITSUO
分类号 G06F9/48;G06F9/46 主分类号 G06F9/48
代理机构 代理人
主权项
地址