发明名称 ARRANGEMENT OF CELLS
摘要 PURPOSE:To relieve concentration of wirings when cells of the plural number are to be arranged regularly on a master slice system substrate by a method wherein idle cells having no logic function are provided in addition to actual cells having logic functions as cells, and the idle cell and the actual cell are exchanged as occasion demands. CONSTITUTION:Bonding pads 2, and buffer circuits 3 to transmit inside the outside signals of an LSI, or to perform reverse action thereof are formed on a semiconductor chip 1. The lines 4 of cells loading the cells are arranged regularly extending over the plural number of stages in the circuits 3 thereof, actual cells having logic functions are accommodated in some cells, and idle cells having no logic function are accommodated in the other cells respectively. At this construction, the fellow actual cells 5 are connected by intercell connecting wires 6 to be accommodated in the prescribed cells 4, and the cells 4 accommodating no actual cell 5 are let lie idle as the idle cells 4. Accordingly, the cells are dispersed as not to generate concentration of wirings, and wiring supplementing work is reduced.
申请公布号 JPS59182539(A) 申请公布日期 1984.10.17
申请号 JP19830055080 申请日期 1983.04.01
申请人 HITACHI SEISAKUSHO KK 发明人 YUYAMA YASUSHI;TAKECHI MAKOTO
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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