| 摘要 |
PURPOSE:To reduce the data transfer time and also to save data storage capacity by adopting a compressed from not including a dummy bit to a data transmitted and received between a CPU and a tester. CONSTITUTION:The CPU1 treats the 2nd data where a dummy data is interpolated in an effective data and a device to be tested treats the 1st data comprising only the effective data. A pattern memory 3 stores the 2nd data. An expansion/compression control circuit 2 provided between the CPU1 and the pattern memory 3 has an identification table storing identification information identifying each of the effective data and conducts the converting processing between the 1st and the 2nd data in response to the stored identification information. |
