| 摘要 |
PURPOSE:To generate always a timing signal having sufficient pulse width and level even if an input signal is held in the intermediate level, by constituting a circuit so that transfer gates are not switched before input signals are settled. CONSTITUTION:Input signals A and B are received by two inverters consisting of FETs Q16, Q17, Q18 and Q26, Q27, Q28 subjected to push-pull connection, and output signals a3 and b3 are inputted to delay circuits, and an FETQ19 whose gate a signal b5 is inputted to is connected in parallel to the output of an inverter consisting of FETs Q13 and Q14, and an FETQ29 whose gate a signal a5 is inputted to is connected in parallel to the output of an inverter consisting of FETs Q23 and Q24, and transfer gates Q15 and Q25 are not switched before input signals A and B are settled, and an output signal C becomes a one shot signal which is switched from the high level to the low level a circuit delay time after input signals A and B are changed and settled. |
