| 摘要 |
PURPOSE:To limit disturbance of phase due to momentary break of reference timing to a minimum by counting the period of synchronizing reference timing obtained by retiming reference timing by a clock in a unit of clock and processing. CONSTITUTION:A digital frequency error detecting circuit 2 receives clock CK from a digital frequency control clock generating circuit 1 by a retiming circuit 21 and a quadruple counting circuit 22. The circuit 2 makes retiming of reference timing TM, and generates synchronizing reference TM of time width of 1CK unit and relative delay change is within 1CK unit time for rising time of the reference TM, and inputs to a delay circuit 26 and AND circuits 24, 25. The circuit 26 delays the input signal by 2CK, resets the circuit 2 to phase 2. The circuit 22 counts the period of synchronizing reference TM in CK unit. This is divided by 4 and according to remaining +1, -1, pulse corresponding to phases 1, 3 is generated by a decoder 23. Up and down counting pulse is generated from circuits 24, 25 and inputted to the circuit 1, and generated CK of the circuit 1 is synchronized to reference TM. |
