| 摘要 |
<p>PURPOSE:To obtain a synchronous clock generating circuit with high precision and high speed by constituting the circuit of an FF that works at the changing point of a row of received data, the first counter that divides a high speed clock, and the second counter that uses the output as an input. CONSTITUTION:An FF10 outputs a rectangular reset signal (d) that rises at the fall point of data (a) by inputting of received data (a). A high speed clock signal (b) is inputted to the clock terminal CLK of a counter 20, and the signal (d) is inputted to a clear terminal CLR. A divided signal (e) of signal (b) synchronized to the data (a) is outputted from an output terminal QC and inputted to a clock terminal CLK of a counter 30. The FF10 is reset by the output the output of a logical product 40 of the signal (b) and signal (d). A logical product 50 output signal (f) of the signal (d) and a frame head signal (c) is inputted to the clear terminal CLR of a counter 30, and a clock signal (g) that always rises from the head to the center of effective data part of the received data (a) is outputted from an output terminal of the counter 30.</p> |
