| 摘要 |
<p>The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches (32, 34) that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor (12), a secondary microprocessor (14), off-chip control storage (26) belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage (24). The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines (48, 50) responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the the primary or secondary microprocessors can thereby be transparently latched to main or control storage.</p> |
