发明名称 PHASE LOCKED LOOP TYPE RECEIVER
摘要 PURPOSE:To suppress phase distortion due to an excessive input signal by adding an AGC circuit operated while being not synchronized and preventing the effect of a disturbing wave. CONSTITUTION:The phase of an output signal of an amplifier 3a and that of a signal caused from a signal without distortion which is an output of a frequency converter 1 while being amplified and phase-shifted are compared, an AGC voltage is applied to a variable attenuator 2 via a low-pass filter 8b, a summing amplifier 14 and a switch 15 to control an output signal level of the amplifier 3a while the distortion is minimized. After a phase locked loop is closed, a lock-on signal changes over the switch 15 to supply a normal AGC (incoherent AGC) voltage to the variable attenuator 2.
申请公布号 JPS6064532(A) 申请公布日期 1985.04.13
申请号 JP19830172513 申请日期 1983.09.19
申请人 MITSUBISHI DENKI KK 发明人 BATORI NAOYA
分类号 H04B1/16;H03J5/02;H04L7/033 主分类号 H04B1/16
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