| 摘要 |
PURPOSE:To reduce steady phase errors by controlling the characteristics of an LPF so that the DC gain is set at a finite level in a non-locked mode of a PLL and then increased after the PLL is locked. CONSTITUTION:A phase comparator 1 compares a horizontal synchronizing signal H-SYNC with a pulse obtained by shifting a horizontal pulse PH obtained from a flyback transformer 4 is a TV receiver through a 90 deg. shifting circuit 5. The phase error output obtained from the comparison is applied to a VCO3 via a lead lag filter 2 in the form of the control voltage. Both the horizontal synchronizing signal and the horizontal pulse undergo the phase comparison through a multiplier 6. Then a lock/non-lock detecting circuit 7 detects a locked or non- locked state of a PLL loop. For the characteristics of the filter 2, the DC gain has a finite and incomplete integration form in a non-locked mode of the PLL loop and then changed to an infinite and complete integration form in a locked mode respectively. This attains a quick lock-in action and reduces steady phase errors in a locked mode of the PLL loop. |
