发明名称 MEMORY SYSTEM OF MULTIPROCESSOR
摘要 <p>PURPOSE:To attain high grade function of a system by storing a multiplex program and input/output information to a local memory to decrease the access frequency from a processor to a common memory. CONSTITUTION:When a control signal of a processor 4 and a DMA circuit 8 is outputted to a memory access control circuit 7, the memory access control circuit 7 discriminates an sccess destination whether it belongs to a common memory 1 or a local memory 5 based on the address information transmitted from the processor 4 or a DMA circuit 8. Then the address signal and the other memory control signal are transmitted to a memory of access destination. An address space specific to each processor is divided into the common memory 1 and the local memory 5 and the address space assigned to the common memory side is limited to a specific area storing a communication area between processors between the processor and the other processor and a specific area storing the system information.</p>
申请公布号 JPS60173655(A) 申请公布日期 1985.09.07
申请号 JP19840013109 申请日期 1984.01.27
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 NAKAYAMA RIYOUHEI;OZAWA KAZUYUKI;FUCHIZAWA HIROTAKA;NAKAMURA TAICHI
分类号 G06F15/17;G06F12/00;G06F12/06;G06F13/36;G06F15/167 主分类号 G06F15/17
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