发明名称 SIMULTANEOUS INSTRUCTION SYSTEM
摘要 PURPOSE:To secure symultaneous instruction by sending a terminal reset signal out of a key station and placing a terminal station in a waiting state forcibly at the start of symultaneous instruction, and then sending a symultaneous instruction. CONSTITUTION:When symultaneous instruction is started from a symultaneous instruction board 1, the controller 2 of the key station sends the terminal station reset signal 9 through a radio device 3 to initialize all terminal stations forcibly. The symultaneous instruction signal is sent out and then symultaneous instruction content is sent out. Therefore, even if some terminal is in use, it is initialized forcibly, so the symultaneous instruction is received securely and processed.
申请公布号 JPS615635(A) 申请公布日期 1986.01.11
申请号 JP19840125225 申请日期 1984.06.20
申请人 HITACHI DENSHI KK 发明人 TORIYAMA KENICHI
分类号 H04B7/26;(IPC1-7):H04B7/26 主分类号 H04B7/26
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