| 摘要 |
PURPOSE:To improve the wiring connection in wiring region in case basic element columns are traversed by a method wherein master chips themselves of semicustom device are composed of two layered wirings while conductive layer patterns composed of upper and lower layers traversing basic element columns are provided. CONSTITUTION:Master chips of gate array are composed of two layered wirings while gate electrodes G are composed of lower wirings. Besides, auxiliary wirings B1 are formed of upper wirings on the gate electrodes G through the intermediary of silicon oxide films. Through these procedures, the wiring concentration in wiring region may be improved remarkably in case basic element columns are traversed. |
