| 摘要 |
PURPOSE:To obtain a VCO circuit without having any variance in the input voltage versus output frequency characteristic even if a process parameter is in variance by constituting the titled circuit with the 1st-3rd VCOs having respectively the 1st-3rd input terminals and an operational amplifier. CONSTITUTION:The VCO 31-33 have respectively the 1st input terminal CONT, the 2nd input terminal OFFSET and the 3rd input terminal GAIN. The voltages fed to each input terminal and an output signal frequency fout have the relation of (VCON+VOFFSET)XVGAINproportional fout. Reference voltages VL,VH are respectively to CONT terminals of the VCOs 31,32, the outputs are compared with reference frequencies FL,fH by phase comparators PDs 34,35 respectively, its error signal is fed to an OFFSET terminal of the VCOs 31,32 via LPFs 35,37 to form a phase locked loop and inputted to inverting/non-inverting terminals of the operational amplifier 38. An input signal V4din controlling the output frequency and an output of the LPF 37 are fed to the VCO 33, an output Va of the amplifier 38 is impressed to the Gain terminal of each VCO to output a stable frequency against the input voltage of the VCO 33. |
