| 摘要 |
PURPOSE:To prevent generation of a wide side band by adding and processing counts of a high frequency clock pulse being an integral number multiple of a carrier frequency and a clock pulse having a frequency in response to a transient period due to the change in a modulation signal. CONSTITUTION:A counter 1 counts repetitively a clock pulse PC1 having a frequency being N times of the carrier frequency fr of a PSK signal and inputs an output (a) to an adder 6. An N/2 counter 5 counts a clock pulse PC2 having a frequency fs when the logical value of a binary modulation signal SM changes from 0 to 1, subtracts the pulse PC2 when the signal SM changes from logical 1 to logical 0 and inputs the output C to the adder 6. When the signal SM is logical 0, the output of the counter 5 is 0, the output (d) of the adder 6 is the same as the output (a), which is subjected to DA conversion 8 via a memory 7 and a PSK signal SPS having the frequency fr is outputted via an LPF9. When the SM is logical 1, the signal C reaches the highest value, which is added to the signal (a) and the signal SPS shifted by 180 deg. is outputted. When the signal SM changes, the output of the counter 5 changes gradually and the side band is not spread. |
