| 摘要 |
PURPOSE:To achieve a higher operability, by providing a shift register for receiving output signals of first and second memory means, a gate means, first and second latch means and a control means for controlling the shift register. CONSTITUTION:A logic tester is equipped with a shift register 3 for receiving output signals from first and second memory means 30 and 32, a gate means 20 and control means 14, 48 and 60 for controlling the shift register 38. When first and second switches are turned OFF while the gate means 20 is turned OFF, logical input signals fed to first and second terminals 10 and 22 can be memorized into first and second memory means separately. When the shift register 38 is operated in the parallel input/series output mode, the memory contents can be outputted at the speed doubling the max. reading speed thereby achieving a higher operability. |
