| 摘要 |
PURPOSE:To reduce an ineffective waiting time of a processing part, and to shorten the processing time by utilizing a response waiting time of the time when executing an input/output instructon, and executing the processing of other program level. CONSTITUTION:A title device is provided with a level 1 inhibiting FF13 which is set by AND of a level 1 running signal 21 and an input/output instruction executing signal 19, and reset by an input/output instruction completing signal 20 from an adaptor. Also, it is constituted so that AND of an output of a level 1 signal holding FF11 for holding a level 1 signal 17 from the adaptor, and a logical inverting signal of the level 1 inhibiting FF13 becomes a level 1 inpt logic of an interruption controlling circuit 10. In this way, when an input/output instruction is executed in the course of running of a level 1, the level 1 signal is inhibited. At that time, if a level 2 whose priority order is low is requested, a level 2 runs, and it is reset to the level 1, when a type 1 adaptor issues an input/output instruction completing signal. |
