发明名称 LOGICAL SIMULATION DEVICE
摘要 PURPOSE:To increase the effective capacity of a history memory substantially by erasing an input vector sequence before an initialization sequence is detected from the history memory when the initialization sequence is detected during simulation. CONSTITUTION:When the simulation is started, contents of the history memory 202 are read out successively and contents of an initialization sequence memory 302 are also read out. At this time, comparators 307 and 308 check whether or not the contents of a history memory address register 200 is larger than those of an initialization sequence counter 303 and whether or not readout data of the memory 202 is equal to readout data of the memory 302; when they are equal, a comparator 309 is used to check whether or not an initialization sequence memory address register 300 are equal to those of the counter 303. When they are equal, the value of the counter 303 is set in the register 200 and the last input vector sequence is erased from the memory 202.
申请公布号 JPS61201347(A) 申请公布日期 1986.09.06
申请号 JP19850041103 申请日期 1985.03.04
申请人 HITACHI LTD 发明人 MORITA MASATO;MIYOSHI MASAYUKI
分类号 G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/25
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