发明名称 DYNAMIC TYPE RAM
摘要 PURPOSE:To make an action multifunctional and to make the action highly speedy by counting a pulse in accordance with a column address strobing signal, having a multiplexer function at an address buffer and receiving selectively an address signal from an external terminal and an internal address signal. CONSTITUTION:When an expanded control signal, the inverse of EX is made into an L level, a control signal, the inverse of phiex comes to be an L level, phiex comes to be a H level, the gate of an address counter circuit COUNT is closed, and the address signal from the external terminal is made invalid. The address signal, the inverse of ai is received in accordance with the address fetched to COUNT. Next, a column address strobing signal, the inverse of CAS is made into a H level, COUNT executes a stepping action, indicates the next address and an address signal ai', etc., are sent a column decoder C-DCR. Consequently, when the signal, the inverse of CAS is made into an L level, the column is changed over and the next reading output signal is sent to an external terminal Dout. Hereinafter, the continuous reading action with the inverse of CAS as a clock signal is executed.
申请公布号 JPS61253697(A) 申请公布日期 1986.11.11
申请号 JP19850095479 申请日期 1985.05.07
申请人 HITACHI LTD 发明人 SATO KATSUYUKI
分类号 G11C11/401;G11C11/34 主分类号 G11C11/401
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