SIGNAL DELAY CIRCUIT

摘要

PURPOSE:To obtain a delay circuit in which fixed pattern noise is not visually prominent by selecting N set as an appropriate number when a video signal is sampled and is converted to N-number of parallel data and is delayed at N-number of delay circuits. CONSTITUTION:The video signal inputted to an input terminal 1 is sampled at a multiplexer 2 and is converted to N-number of parallel data. The output is delayed by approximately one horizontal period time at N-number of delay circuits 3-1-3-18 and is converted to serial data at a multiplexer 4 and is outputted from a terminal 5. Assuming that a sampling number in one horizontal period time is M and a numeric vale [M/N] is set as the maximum integer not exceeding a numeric value M/N, by selecting the value of N as the minimum value out of values that M-[M/N]XN and N-{M-[M/N]XN} are greater than 2 and also N/(M-[M/N]XN or N/(N-{M-[M/N]XN}) is a decimal value greater than 2.5, it is possible to obtain the delay circuit in which the fixed pattern noise is not excessively prominent visually.