发明名称 VIDEO DEFEAT CIRCUIT
摘要 PURPOSE:To enable observation of the content of a video program at the time of consecutive channel switching which is impossible to observe in conventional case where the video-defeating is not released by providing an integrating circuit in parallel with a conventional defeating circuit. CONSTITUTION:The integrating circuit consists of a resistor 1 and a capacitor 2. The intersecting point between the two parts is connected to the base of a switching transistor 3. The collector of the transistor 3 is pulled up by the power supply source through a resistor 5. In such way, the defeat-releasing circuit is constituted. The defeating circuit is not actuated by a single defeat pulse, and is not actuated by consecutive defeat pulses, the video program content during the rapid tuning time is made able to be observed which is impossible to observe conventional case where the defeating action is not released.
申请公布号 JPS61264973(A) 申请公布日期 1986.11.22
申请号 JP19850107429 申请日期 1985.05.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AYA MASAKAZU;TAKAYAMA NORITSUGU
分类号 H04N5/44;(IPC1-7):H04N5/44 主分类号 H04N5/44
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