发明名称 MULTI-CHIP PACKAGE SUBSTRATE
摘要 PURPOSE:To provide low impedance of 50-100OMEGA as the characteristic impedance of the microstrip lines of a multi-chip package substrate even if the width of the line is miniaturized, by providing a very thin silicon oxide film (or silicon nitride film) on a silicon substrate, whose impurity concentration is very high, and using the silicon oxide film as a dielectric material. CONSTITUTION:On a silicon substrate 13, a silicon oxide film 15, whose thickness is, e.g., 1-5mum, is provided. A wiring pattern 21 including microstrip lines 17 and wirings 19 are provided on the silicon oxide film 15. The microstrip lines 17 comprise suitable metal material. The wiring 19 is wider than the microstrip line 17 for external terminals, power source lines and the like. A part of the silicon oxide film 15 is removed in order to reduce grounding inductance, and a through hole 13 reaching the silicon substrate 13 is provided, in a package substrate 11. The desired circuit part can be grounded to the silicon substrate through said through hole 23 are required.
申请公布号 JPS6215850(A) 申请公布日期 1987.01.24
申请号 JP19850154515 申请日期 1985.07.13
申请人 OKI ELECTRIC IND CO LTD 发明人 UENISHI KATSUZO
分类号 H01L23/52;H01L23/14;H05K1/05;H05K3/40 主分类号 H01L23/52
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