| 摘要 |
PURPOSE:To facilitate easy processing when the exceptional conditions are produced by preventing such a case where the next instruction address is loaded to an instruction counter from a register for the next instruction address when the exceptional conditions are detected. CONSTITUTION:The instruction length is added to the contents of an instruction counter 2 by an adder circuit 3 and the next instruction address is produced and held by a next instruction address register 10 with the replacement timing of the counter 2. If a flag 7 showing the exceptional conditions is not set at said timing, the contents of the register 10 are loaded to the counter 2 at the time point of the next control cycle by the signal of a control line 11. If the flag 7 is not set at said timing, the exceptional condition detecting signal 13 is turned on to prevent the signal of the line 11, the previous contents of the next instruction address of the interrupted instruction are held as they are by the counter 2. Thus it is prevented to proceed to the next instruction address and therefore the easy processing is possible when the exceptional conditions are produced. |
