发明名称 SYSTEM FOR PREVENTING TRANSIENT INDUCED ERRORS IN PHASE LOCKED LOOP
摘要 A system for minimizing synchronization errors in a phase-locked loop having a sequential phase detector for determining the phase difference between the output of the VCO of the phase-locked loop and a periodic control signal. Control circuitry is provided so that the control signal is enabled as an input to said sequential phase detector for a relatively short time window which comprises a small fraction of the control signal cycle period beginning just before a control signal is anticipated and the signal is disabled for the remainder of said control signal cycle period. Provision is made for the phase detector to process only the first control signal in any given enable time window. Additional circuitry is provided to disable the control circuitry when the phase locked loop is detected to be out of lock.
申请公布号 AU558935(B2) 申请公布日期 1987.02.12
申请号 AU19820090501 申请日期 1982.09.23
申请人 HONEYWELL INC 发明人 KACKMAN, G.M.
分类号 H03L7/08;H03L7/191;H04L27/12 主分类号 H03L7/08
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