发明名称 DECODER CIRCUIT
摘要 PURPOSE:To reduce the deterioration in S/N of a reproducing high frequency signal by applying correction making a sample value of a word causing a code error zero when the code error takes place at a straight PCM mode. CONSTITUTION:A data such as a mode data, a range data or a compression data is fed serially to an input terminal 1. The data is inputted to a multiplexer 3 via an error detection circuit 2 and they are separated. When an error is detected from th error detection circuit 2, an error signal is fed to a correction circuit 5 from the multiplexer 3. The correction circuit 5 consists of a mean value interpolation circuit 5b and a '0' replacing circuit 5a. The '0' replacing circuit 5a applies a processing making the word sample causing a code error zero. When a straight PCM mode is detected from the mode data fed from the multiplexer 3, the straight PCM detection circuit 4 throws a switch 10 to the position of the '0' replacement circuit 5a. In the straight PCM mode, since the handled frequency is high, the interpolation of '0' replacement reduces noise than the mean value interpolation.
申请公布号 JPS62112425(A) 申请公布日期 1987.05.23
申请号 JP19850252367 申请日期 1985.11.11
申请人 SONY CORP 发明人 AKAGIRI KENZO;NISHIGUCHI MASAYUKI
分类号 H03M7/00;H03M3/00;H03M7/28;H03M7/30;H03M13/00 主分类号 H03M7/00
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